1. Field of the Invention
The present invention relates to a system on a programmable chip. More specifically, the present invention relates to methods and apparatus for accessing a memory on a programmable chip.
2. Description of Related Art
In embedded microprocessor systems, processor performance is often supplemented by incorporating hardware accelerators to improve time-critical portions of algorithms. However, these systems usually do not come close to achieving the theoretical performance improvements. The hardware accelerator and processor need to frequently exchange data. As a result, the raw performance gain is diluted by the overhead incurred for performing often inefficient memory read or write accesses.
Generally there are three schemes for sharing and arbitrating memory in a hardware-accelerated system. In one example, the accelerator controls access to memory. In another example, memory is shared and accesses are arbitrated. In still another example, the processor controls access to memory.
If the accelerator controls accesses, then data is copied from the processor to the accelerator and back again. If the memory is shared, the processor and hardware accelerator use somewhat generic bus interfaces. This is likely to affect performance as arbitration is not optimal and is likely to be affected by other components in the system.
Consequently, it is therefore desirable to provide improved methods and apparatus for improving data access efficiency. In one example, it is desirable to provide logic and circuitry to improve read/write access efficiency of a processor memory.